Niteya

Niteya

Speeding up computing@VT

Portfolio

Niteya Shah

Phone +1 540-250-
E-mail niteya.56@gmail.com
niteya@vt.edu
VISA Indian Student with F1 visa

EDUCATION

M.S in Computer Science from Virginia Tech (expected) 2021-
Relevant Coursework
Numerical Analysis and Software Multiprocessor Programming
B.Eng. Computer Science from Vellore Institute of Technology 2016-
Relevant Coursework
Artificial Intelligence Machine Learning Data Mining
Parallel and Distributed Computing High-Performance Computing Data Structures and Algorithms
Business Analytics for Engineers Soft Computing Natural Language Processing

EXPERIENCE

Graduate Researcher August 2021-Present SyNeRGy Lab and SEEC Center Supervisor: Dr Wu Feng Userspace Paging Optimization

  • Study the effect of tuning paging parameters on applications with different characteristics using UMAP
  • Identify optimal paging parameters in the user space using autotuning.

Global Analysis of Quantum Chromodynamics(QCD)

  • Profile QCD carpentry code to find critical sections and linearization points.
  • Improve performance of code by parallelization, optimization, and refactoring leading to a two-fold speedup.

Data Scientist May 2020 - July 2021 Tiger Digital Advertising, Vadodara

  • Analysed data to gain insights, and learn patterns and trends.
  • Tested products for market feasibility and identify customer bases with exploratory campaigns by using data driven decisions.
  • Translated research to standard operating procedures and create associated documentation for others to follow and extend.

INTERNSHIPS

DevOps Engineering Intern May 2019 - July 2019 Tiger Digital Advertising, Vadodara

  • Executed automated desktop deployments.
  • Performed ongoing performance tuning, hardware upgrades, and resource optimization.
  • Monitored performance of system architecture, storage methods, and management system software leading to modifications and adjustments.

OPEN SOURCE CONTRIBUTIONS

  • Contributor to CuPy, an A NumPy-compatible matrix library accelerated by CUDA
  • Contributor to Mlpack, a machine learning library in C++
  • Contributor to ensmallen, a flexible C++ library for efficient numerical optimization
  • Contributor to Numba, a high performance Python compiler

PROJECTS

Face Recognition using Map Locking Winter 2019

Undergrad Thesis

Supervisor : Dr. Kannan A, Vellore Institute of Technology

  • Designed and developed a custom loss function that better extracted information from the final feature representation
  • Cleaned and pre-processed the VGGFace2 dataset with 3.3 million images
  • Designed a model architecture based on MobileNet and trained the model using both offline and online learning
  • Achieved an accuracy of 98.7% on the test segment

Fluid Simulation using CUDA Fall 2019

  • Designed and developed a fluid simulation engine using Smoothed-particle hydrodynamics, accelerated by CUDA.
  • Achieved a 40-fold speedup over a serial implementation.
  • Engine can simulate 10 million particles in real time and show results via matplotlib.

Survey of Load-Balancing Algorithms used in Geometric Space Fall 2019

  • Performed extensive review of Multi-Jagged, RCB and RIB load-balancing algorithms in the Zoltan package which is a part of the Trilinos project.
  • Compared the performance improvements and error growth caused by spatially partitioning the datasets using the algorithms.

Gujarati Speech Recognition Winter 2018

  • Developed a speech-to-text model for the Gujarati Language.
  • The model architecture was composed of bidirectional gated recurrent units and used connectionist temporal classification to estimate correctness and was trained on the Microsoft Speech Recognition Dataset.
  • The model achieved 85% accuracy on the test segment.